1. Field of the Invention
The present invention is directed to signal transmission and reception, and in particular, to an apparatus that reduces pattern jitter and a method using the same.
2. Background of the Related Art
In general, when a signal is transmitted and received between a transmitting terminal and a receiving terminal in data communications, the signal transmitted from the transmitting terminal is received by the receiving terminal, and then, a timing phase of the received signal must be recovered. Recovering the timing phase implies finding an exact sampling timing from the received signal to regenerate the exact transmitted signal.
For example, in accordance with a nonlinear spectral line timing recovery, which is popularly used in an analog field, a carrier is removed from a received signal (in an analog type), and a tone signal is generated by squaring the received signal with its carrier removed. A timing phase signal of the received signal is generated by filtering the tone signal, and thus, the transmitted signal is regenerated.
For example, in accordance with a discrete-time nonlinear spectral line timing recovery, which is utilized in a digital field, an oversampling is carried out on a received symbol signal. A timing phase signal of the received signal is generated by carrying out a filtering or a digital fourier transform DFT on the oversampled signal, and thus, the transmitted signal is regenerated.
When the timing phase of the received signal is recovered by the above-described methods, even if a channel noise is small, a timing error occurs that makes it difficult to find an exact sampling timing of the received signal. In particular, when the transmitted signal from the transmitting terminal has a pattern of xe2x80x9c. . . 1, 1, 1, . . . xe2x80x9d or xe2x80x9c. . . xe2x88x921, xe2x88x921, xe2x88x921, . . . xe2x80x9d, even if a nonlinear operation unit for squaring the received signal of the receiving terminal serves to generate a nonlinear signal, a tone signal of the nonlinear signal is small, and thus, noise is inserted into the timing phase signal. The error is called a xe2x80x9cpattern jitterxe2x80x9d or a xe2x80x9cself-noisexe2x80x9d.
A related art apparatus for reducing the pattern jitter will now be described. FIG. 1 is a schematic view of the related art apparatus for reducing the pattern jitter. The apparatus includes an A/D (analog/digital) converter 10 receiving a symbol signal DIN and sampling the N symbol signals with a sampling frequency f. The A/D (analog/digital) converter 10 outputs a received signal D1, which is convoluted with a raised cosine wave. A prefilter 12 filters the received signal D1 and outputs a first filtering signal D2. A nonlinear operation unit 14 squares the filtering signal D2 to output a nonlinear signal D3, and a bandpass filter 16 bandpass-filters the nonlinear signal D3 to output a second filtering signal D4. A phase detector 18 detects a phase of the second filtering signal D4, and outputs a timing phase signal DOUT.
A method for reducing the pattern jitter using the related art apparatus for reducing the pattern jitter will now be described. FIG. 2 illustrates a raised cosine wave signal inputted to the prefilter and a quasi locally symmetric wave signal QLS outputted from the prefilter to show a principle for reducing the pattern jitter with the related art apparatus. When the raised cosine wave signal RC is inputted to the prefilter 12, the signal outputted from the prefilter 12 is the quasi locally symmetric wave signal QLS, which is symmetric to a peak or a zero-crossing of the raised cosine wave signal RC and has many tone signals.
FIGS. 3A to 3C respectively illustrate signals inputted to or outputted from the related art apparatus for reducing the pattern jitter. When the symbol signal DIN is a binary type shown in FIG. 3A that is oversampled 8 times higher than the rate of the symbol signal and convoluted with the raised cosine wave signal RC by the A/D converter 10, the received signal D1 is outputted from the A/D converter 10 as shown in FIG. 3B. At this time, the symbol signal and the received signal D1 have pattern jitter because signals that identically have a positive sign and an amplitude value of xe2x80x981xe2x80x99 are repeated for a symbol time 8 to 32 and a symbol time 48 to 80 as shown in FIG. 3A. Therefore, in accordance with the above-described functions of the prefilter 12, the nonlinear operation unit 14 receives the first filtering signal D2 in the quasi locally symmetric wave signal QLS type, which has a property of limiting a band and is locally symmetric to each point indicating integer times of a symbol period as shown in FIG. 3C. Here, the first filtering signal D2 has a value of xe2x80x980xe2x80x99 (zero) on the point indicating the integer times (excluding xe2x80x980xe2x80x99 (zero)) of the symbol period. Accordingly, an interference between the symbol signals is removed. However, the interference still remains on the other points.
The nonlinear operation unit 14 outputs the nonlinear signal D3 only having a positive value by squaring the first filtering signal D2. The bandpass filter 16, which has a center frequency identical to a frequency of the symbol rate, receives the nonlinear signal D3 and outputs the second filtering signal D4 in a sinusoidal wave type.
The phase detector 18, which receives the second filtering signal D4, serves to output the timing phase signal to be regarded as an optimal sampling timing of the symbol signal. The optimal sampling timing is a timing corresponding to a peak or a zero-crossing of the second filtering signal D4. In accordance with the related art method for recovering the timing phase by utilizing the prefilter, the pattern jitter can be reduced by generating a signal in the quasi locally symmetric wave signal QLS type to provide sampling timing information regardless of a pattern of the symbol signal.
However, the related art apparatus and method have various disadvantages. The prefilter of the related art requires a large amount and complex hardware. That is, the prefilter including M taps needs as many multipliers as the number of the taps (M), Mxe2x88x921 adders and Mxe2x88x921 memory devices, which make the related art system bigger. This disadvantage is especially severe when a very large scale integration VLSI is embodied because the multiplier consumes a large amount of electricity as well as takes a large portion of a chip. In addition, the related art method for recovering the timing phase has another disadvantage in that the number of the operations carried out on the symbol signal increases in proportion to the number of the taps in the prefilter.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the present invention is to provide an apparatus and method for reducing pattern jitter that substantially obviates one or more disadvantages caused by limitations of the related art.
Another object of the present invention is to provide an apparatus for reducing a pattern jitter of a symbol signal and a method using the same that determines a timing phase of the symbol signal.
Another object of the present invention is to provide an apparatus for reducing a pattern jitter that requires reduced hardware or consumes a less power.
Another object of the present invention is to provide an apparatus and method that can reduce a specific pattern jitter of a symbol signal by using a local symmetry forcing wave generating unit when a timing phase of the symbol signal is recovered.
In order to achieve at least the above-described objects in a whole or in parts, there is provided an apparatus for reducing a pattern jitter according to the present invention that includes a demultiplexer that receives an input including a preamble signal and a data signal from an analog/digital (A/D) converter; a nonlinear operation unit that receives the preamble signal; a locally symmetric wave generating unit that receives the data signal; a buffer memory that receives an output signal from the nonlinear operation unit and an output signal from the locally symmetric wave generating unit; and an input signal controller that receives a control signal outputted from the A/D converter and outputs an input control signal to control the buffer memory and the demultiplexer.
To further achieve the above objects in a whole or in parts, there is provided an apparatus for reducing pattern jitter according to the present invention that includes a local symmetry forcing wave generator that receives the received signal, a control signal and a previous timing phase signal, and outputs a local symmetry forcing wave signal including more tone signals than the received signal, a bandpass filter that filters the locally symmetry forcing wave signal and outputs a filtering signal, and a phase detector that detects a phase from the filtering signal and outputs a timing phase signal.
To further achieve the above objects in a whole or in parts, there is provided a method for reducing pattern jitter according to the present invention that includes a preamble signal and a data signal, including initializing a timing phase signal using the preamble signal included in the received signal, discriminating between the preamble signal and the data signal included in the received signal using a control signal, performing a nonlinear operation on the preamble signal when an inputted signal is discriminated as the preamble signal, inputting the data signal when the inputted signal is discriminated as the data signal, comparing a sign of the data signal with that of a previous timing signal, inserting a prescribed value between the data signal and a previous data signal when the data signal and the previous timing signal have an identical sign, performing a nonlinear operation on the data signal when the sign of the data signal is different from that of the previous timing signal, bandpass-filtering on a nonlinear operation signal generated by the performing steps, and detecting a phase of the bandpass-filtered signal and outputting a sampling timing phase signal of a symbol signal, wherein the received signal is based on the symbol signal.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.